Thursday, 21 November 2024

Key Notes

Ludovic GOUX - IMEC, Belgium

Non-Volatile Memory technologies for Storage Class

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Sep 21
14:15 - 15:00

For more than 40 years the evolution of Non-Volatile Memories (NVM) has mostly relied on the downscaling of floating-gate Flash memories. Today the scaling of NAND Flash is facing physical limitations below 20nm technology node, however the successful further density increase of Flash has been clearly demonstrated recently through 3D integration of Vertical NAND structures, which clearly consolidates the domination of this technology in high-density applications.
On the other hand, the latency/performance gap between Flash and DRAM has also increased further over the last years. This opens up an application space for emerging memory concepts that hold the promise of reaching a better trade-off. In this space, Spin-Transfer Torque Magnetic RAM (STT-MRAM) is a serious candidate in the Memory-mapped SCM (M-SCM) space, having potential to partially replace DRAM in low-power applications. On the other side of the SCM space, called the Storage-mapped SCM (S-SCM) space, Resistive RAM (RRAM) technologies are intensively developed as they promise excellent scalability together with low fabrication cost.
In this keynote we will review the assets of NAND Flash, STT-MRAM, and RRAM technologies, as well as some key technological challenges they are currently facing. Specific developments carried out at imec will be described. In a second part we will elaborate more extensively on the various developments within the RRAM family, where sub-categories like Oxide RAM (OxRAM), Conductive-Bridge RAM (CBRAM) or Self-Rectifying Cells (SRC) have emerged and have broadened further the exploration and application scope. We will review some achievements reached at imec in material developments and technological advances in OxRAM, CBRAM and SRC concepts, in particular with respect to cell size and current scaling. Strong reliability challenges (variability, endurance, retention) are still ahead, and will need to be addressed statistically on array level. Continued material research and process development in particular will be key to determine the future of these technologies.

 

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