Localised SOI for monolithic integration of silicon photonics, MEMS and standard CMOS-IC

Marco Balucani, CNIS-Sapienza University of Rome & RISE Technology

Today’s silicon photonics is mainly a hybrid technology. The majority of Integrated circuits like CMOS, SiGe, SiGe:C are usually built with standard silicon wafers or if Silicon On Insulator (SOI) wafers are used for CMOS, the top silicon (TopSi) layer thickness is usually than 100 nm and the buried oxide (BOX) layer is less than 200 nm. Integrated optical interconnects realized within TopSi on such wafers will suffer from high optical loss into the substrate due to low BOX thickness. High frequency operation for silicon photonics poses another issue for such SOI wafers. In order to allow high frequency modulation (e.g. 25GHz) with low losses for the transmission line driving the SP modulator the substrate must have a very low doping level (i.e. 750 W∙cm), thus increasing the cost of the wafer up to 4 times. Considering this silicon photonics has essentially been based on SOI wafers that are different from those for conventional CMOS electronics: with TopSi 220… 340 nm and significantly thicker BOX of 2000… 3000 nm. But on the other hand, attempts to realize high-speed ICs like processors, memories and/or ASIC devices on silicon photonics SOI substrates will be quite challenging, if not impossible, due to the different device properties, due to thermal dissipation issues and due to the necessity of tight control of SP SOI cross-wafer uniformity.

A novel approach for the monolithic integration of SP, MEMS and IC based on fabrication of localized SOI structures is illustrated. Islands of SOI are created via the porous silicon fabrication process, obtained by localized electrochemical conversion of the substrate. The sensitivity of the porous silicon formation process to substrate doping level is exploited for controlling the geometry of the island and BOX thickness. The expansion of the application range for MEMS fabrication is discussed. Possible applications of various porous silicon morphologies like macro and micro-PS are highlighted.

 
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