Tommaso VALI
Micron

Tommaso is Senior Director at Micron Semiconductor Italy and has the responsibility of the Avezzano, Padova and Catania Design centers for the design on NVM memories in Europe.
He  received a degree in electronic engineering at university of Rome “La Sapienza” in 1987, since then worked at Texas Instruments and moved T.I.  Avezzano R&D department as designer engineer of MOS circuits in 1994.

He became Senior designer and Distinguished Member of Technical Staff at T.I in 1996. In 1998, following Micron Technology Inc. acquisition of all T.I. memory business, Tommaso had increasing responsibilities in the design center as team leader and design manager for Wireless NOR.

From 2004 Director of Avezzano design center for NAND design.
In 2008 Padua design center was set up.
In 2010 the team released the first 32Gb 3bpc NAND memory at 32nm in the industry (presented at 2010 ISSCC, S.Francisco).
Since 2015 in charge of Catania design center too.
In 2015 the team released a 256Gb 2b/cell 3D NAND and a worked to a 768Gb 3b/cell 3D Floating Gate NAND Flash memory  (presented at 2016 ISSCC , S.Francisco)

Tommaso is also a regular lecturer to the University of L’Aquila to cover topics about Nand Flash design to post graduate students of Electronics Engineering School.
He holds more than 50 patents and is author and coauthor of 8 papers in the field of non N.V.M.

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